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Please use this identifier to cite or link to this item: http://ir.calis.edu.cn/hdl/530500/4707

Title: Wu’s Characteristic Set Method for SystemVerilog Assertions Verification
Authors: School of Software of Dalian University of Technology, Dalian 116620, China
School of Computer and Information Technology, Beijing Jiaotong University, Beijing 10044, China
School of Electronic and Information Engineering, Lanzhou Jiaotong University, Lanzhou 730070, China
4Guangxi Key Laboratory of Hybrid Computation and IC Design Analysis, Guangxi University for Nationalities,Nanning 530006, China
Xinyan Gao
Ning Zhou
Dakui Li
Keywords: SystemVerilog
Synchronous Digital System
Polynomial Set
Sequence Operator Modeling
Wu’s Characteristic Set Method
Issue Date: 2013
Publisher: Journal of Applied Mathematics
Citation: Journal of Applied Mathematics, 2013, Vol.2013
Abstract: We propose a verification solution based on characteristic set of Wu’s method towards SystemVerilog assertion checking over digital circuit systems. We define a suitable subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We present an algorithm framework based on the algebraic representations using characteristic set of polynomial system. This symbolic algebraic approach is a useful supplement to the existent verification methods based on simulation.
URI: http://ir.calis.edu.cn/hdl/530500/4707
Appears in Collections:期刊论文

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